Static Random Access Memory (SRAM) is used on most System on Chip (SoC) devices. Many hand-held devices, including Internet of Things (IoT) devices, require very low power consumption and long battery life, yet often these devices are required to hold the contents of the SRAM for extended periods of time. When the power to the SRAM is turned off, data stored in the bitcells is lost. However, when the bitcells are idle, i.e., not being read or written, the bitcells can be placed in retention mode, which utilizes much less power. This is possible because the voltage headroom for the SRAM can be reduced during retention mode, as the static noise margin is better when the wordline is OFF than during accesses to the bitcell when the wordline is ON. The reduced headroom leads to a lower leakage current through the bitcells. However, these systems can be heavily duty cycled and are typically energy starved, so even with the reduction in voltage headroom, SRAM leakage during retention mode is a significant proportion of the power budget of any SoC. Accordingly, the usage of power in retention mode is of critical importance.